soc/intel/cannonlake: Fix afterg3 programming

According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC
memory mapped register but not pci config spaces. Change the programming
to affect that difference.

BUG=b:122425492
TEST=Change System Power State after failure to "s5 off", and boot up
onto sarien platform, check the register with iotools mmio_read32
0xfe001020 and bit 0 is set.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e
Reviewed-on: https://review.coreboot.org/c/30945
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions