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authorAndrey Petrov <anpetrov@fb.com>2020-04-20 18:07:08 -0700
committerAndrey Petrov <andrey.petrov@gmail.com>2020-04-24 19:44:00 +0000
commitdddb9a85bd1e9810410f14010f20c9ce2dabfee5 (patch)
treeedc0f2328984b41c2a0f15a414158850b10ebc41 /README.md
parent2f96970e1f4e586a4c5928fefab1bc0f98bc1351 (diff)
soc/intel/xeon_sp/cpx: Work around FSP-M issues
Currently FSP-M does not implement the spec completely, e.g it is unable to use user-provided heap location in CAR. While this is being resolved, this workaround is a stop-gap solution that allows multi-socket usage. TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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