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authorMario Scheithauer <mario.scheithauer@siemens.com>2019-01-29 08:54:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-30 11:01:01 +0000
commit9ca43191ab454c777102f9634b5d40478cd4dc58 (patch)
tree5f6cd88a169851db8bca8dce6c3b6f0daa6b4b21 /Makefile
parentddf84986d540e275cee906933637480f526530a5 (diff)
siemens/mc_apl2: Change SERIRQ mode
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected. By removing this entry from devicetree, the default value (quiet mode) is used. The problem is described in Intel document 334820-007 under point APL47. Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31138 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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