soc/intel/alderlake: Refactor eSOL for late CSE sync text message

This patch extends the eSOL implementation on Alder Lake to render text
messages during late CSE sync (from ramstage).

Currently, the eSOL is limited to the early boot phase (until romstage)
and only displays FSP-M memory training warnings or messages during
early CSE sync (at romstage).

Platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage,
cannot display any eSOL messages, resulting in a brief black screen
during CSE firmware updates.

This patch implements the following logic to scale eSOL for late CSE
sync (at ramstage) without recompiling eSOL code for ramstage:

1. During boot, check if the MRC cache is available. This indicates the
   need for memory/DRAM training and triggers an eSOL message.
2. For CSE lite SKUs (applicable to CrOS), leverage the
   `is_cse_fw_update_required` API to check if the current CSE RW
   firmware version differs from the CBFS metadata file version.
   If so, trigger an eSOL message indicating a CSE sync is required.
3. If either condition #1 and/or #2 is true, the AP firmware renders
   an eSOL text message using LibGfxInit for the Alder Lake platform.

BUG=b:359814797
TEST=eSOL text messages are displayed during CSE sync and FSP updates.

tirwen-rev3 ~ # elogtool list
0 | ... | Log area cleared | 4088
1 | ... | Early Sign of Life | MRC Early SOL Screen Shown
1 | ... | Early Sign of Life | CSE Sync Early SOL Screen Shown
2 | ... | System boot | 197
3 | ... | Memory Cache Update | Normal | Success
4 | ... | System boot | 198
5 | ... | Firmware Splash Screen | Enabled

Change-Id: I1c7d4475ed5cf6888df1beebab0641ee4203b497
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83975
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>

0 files changed, 0 insertions, 0 deletions