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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-07-27 09:05:44 -0600
committerMartin Roth <martinroth@google.com>2017-07-27 21:18:39 +0000
commit7bf860ffedb10a5d69381ad92b3eb7a1169969a9 (patch)
treed4fc93ffa15ca57b5967edde99fdd7be33e69531 /Makefile
parent03e44f46b080022a0c8949b2cc7ba88d587e671e (diff)
soc/amd/stoneyridge: Clarify BAR mask in SPI base
The format of the D14F3xA0 SPI Base_Addr register is different than a traditional BAR. Change the function to preserve any enables already in place. Change the AND mask to remove the reserved field and the enables. Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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