diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-11-05 10:29:24 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-11-16 21:45:36 +0000 |
| commit | b25576fa6368f288f1ce3e34f87894d6cd3859d1 (patch) | |
| tree | a91cc47dba05934a3a94da0070327f556afda75a /Makefile.inc | |
| parent | 571e7f02de2d9e4047c28ace45430a777252cba3 (diff) | |
src/lib/prog_loaders: Add preload_ramstage
This will enable preloading ramstage. By preloading the file into
cbfs_cache we reduce boot time.
BUG=b:179699789
TEST=Boot guybrush to OS and see 12ms reduction in boot time.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'Makefile.inc')
| -rw-r--r-- | Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Makefile.inc b/Makefile.inc index b784f3eee8..f14bc1eb39 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1214,6 +1214,10 @@ cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) $(CONFIG_CBFS_PREFIX)/ramstage-type := stage $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG) +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +$(CONFIG_CBFS_PREFIX)/ramstage-align := 64 +endif cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) |