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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-12-02 16:19:14 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-12-13 13:54:52 +0000
commit1ac0dc164d81f28602668cdb559b44f18dd4227d (patch)
treecd52a6330f2afb8343fbaa37857e3caa7113ed30 /Makefile.inc
parentdcf045918b8584d23e487f70959ebbb2ef4492b6 (diff)
soc/intel/tigerlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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