soc/intel/adl/acpi: add entries for HEC1 and SRAM to DSDT

HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb:

device pci 16.0 alias heci1 on  end
device pci 14.2 alias shared_sram off end

This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel

TEST=Built and tested on brya to confirm errors are not seen.
BUG=b:260258765

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions