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authorFurquan Shaikh <furquan@chromium.org>2016-10-28 14:55:46 -0700
committerFurquan Shaikh <furquan@google.com>2016-10-29 00:23:09 +0200
commit566feddeceb421ba6480bcee94f87bc4c95c6196 (patch)
tree1dc6f059c58d7f3382e497d9690235856a737732 /MAINTAINERS
parent4ef7491b2213555ad71920035b5d08e7798024fb (diff)
soc/intel/common: Add reset.c to postcar
ramstage_cache_invalid which was added in I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112) requires hard_reset to be defined in postcar stage. BUG=None BRANCH=None TEST=Compiles successfully for reef. Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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