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authorFelix Held <felix.held@amd.corp-partner.google.com>2020-04-04 02:48:03 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:28:40 +0000
commitd149f1db69c9ddde793889931ce8fef931d13cd8 (patch)
tree5918951f3b8d9653904523045ed86dababb80558 /MAINTAINERS
parent30322785c446a20bce98e0591eb8fcf0023dcb53 (diff)
soc/amd/picasso: Enable cache in bootblock
Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM setup code to properly enable MTRRs. Add that capability to the bootblock_c_entry() function. In addition, enable an MTRR to cache (WP) the flash boot device and another for WB of the non-XIP bootblock running in DRAM. BUG=b:147042464 TEST=Boot trembyle to payload and make sure bootblock isn't abnormally slow. Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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