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authorArthur Heymans <arthur@aheymans.xyz>2022-05-31 22:00:13 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-06-17 15:27:21 +0000
commit8cd1dfa4ae98a11300113582647552a242cf991b (patch)
treec52cbdacfdde571deccbef4e39c6f65aff365367 /LICENSES
parent5b67ad0a5f7a1ba9d5a4dc46c7d2dec1665f00d7 (diff)
soc/amd/smm_relocate.c: Improve TSEG programming
TSEG does not need to be aligned to 128KiB but to its size, as the MSR works like an MTRR. 128KiB is a minimum TSEG size however. TESTED on google/vilboz. Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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