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authorKarthikeyan Ramasubramanian <kramasub@google.com>2021-10-05 13:57:30 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-10-13 17:37:39 +0000
commit2d17ea4d501c8e0f68813cda80dd6412b10ca0d8 (patch)
treed58219f9780325c10a5b8ae02c56e1235f2995b4 /LICENSES
parent425e73d3f545430884ad2020d56300aae88a1714 (diff)
soc/amd/common/block/espi_util: Refactor eSPI Setup
eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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