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authorMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-10-30 20:58:41 -0500
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-11-02 13:57:18 +0000
commit0daefa54eb361965df2595c2b043666b7800df09 (patch)
treead077cbf44226d28d39d427936e480ad8f76bae7 /LICENSES
parent7d3ababd71031fdb6f0cf08af41b26616efc5006 (diff)
soc/amd/*: Ensure PSP soft fuse bitmask set properly
Commit e728766f4596 ("soc/amd/mendocino: Do not load MP2 Firmware when in RO") added logic to ensure that the MP2 disable soft fuse bit was set for the RO section, but failed to check if the bit was already set otherwise (as it is for non-ChromeOS builds). This caused the bit to appear twice in the PSP_RO_SOFTFUSE_BITS string, and when the string was converted to a series of numeric values and added together, bit (n+1) ended up being set instead of bit n. To mitigate this, use the makefile sort() function to ensure the PSP_[RO_]SOFTFUSE_BITS string does not contain any duplicates before the bitmask is calculated. Apply this to all AMD SoC makefiles where the softfuse bits are added. TEST=build/boot google/skyrim (frostflow). Use a verbose build (V=1) to verify that the correct soft fuse value is passed to amdfwtool for RO and RW_A/B for both ChromeOS and non-ChromeOS builds. Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78823 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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