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authorAndrey Petrov <anpetrov@fb.com>2020-03-22 22:27:44 -0700
committerAndrey Petrov <anpetrov@fb.com>2020-03-26 02:53:26 +0000
commit335384d2b75eb0266c6f13b52e20b2d3bba390ea (patch)
treedc9e6dab2178508915c66e948be2363d0aa36826 /LICENSES
parent403f215cb4e2486d0b89ec97978263948fbc7ce6 (diff)
soc/intel/xeon_sp: Configure P2SB BAR in bootblock
In order to use early serial output we need to enable P2SB BAR0, because that allows PCR access to PCH registers. TEST=tested on OCP Tioga Pass Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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