nb/intel/sandybridge: Use loops on DMI register groups

The DMI link consists of four lanes, grouped in two bundles. Therefore,
some DMI registers may be organized as "per-lane" or "per-bundle". This
can be seen in the DMI initialization sequence as series of equidistant
offsets being programmed with the same value. Make this more obvious by
factoring out the register groups using loops.

With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.

Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

0 files changed, 0 insertions, 0 deletions