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author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2021-01-14 14:54:38 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-20 12:26:42 +0000 |
commit | 92e4ed170232dd6e460be996772f07a26e620677 (patch) | |
tree | d3ae07243c2130e250dfa4594e6b08f5c5ee533e /LICENSES/GPL-2.0-or-later.txt | |
parent | 1bc061ee90bf87b89c93913b9116ad5a842e8b6a (diff) |
mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs
Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.
The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs
TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'
Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'LICENSES/GPL-2.0-or-later.txt')
0 files changed, 0 insertions, 0 deletions