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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-05-28 11:29:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-06 15:31:06 +0000 |
| commit | c162131d00c7f3b8827f9dd08754497c36884123 (patch) | |
| tree | ea84390a3a310920a4231ee11d29c380d3028828 /Documentation | |
| parent | 6b2a54030fe1821a9e7360d3da668e1a710fada0 (diff) | |
superio/common: Add ssdtgen for generic SuperIOs
Add a generic SuperIO ACPI generator, dropping the need to include
additional code in DSDT for SuperIO.
It generates a device HID based on the decoded I/O range.
Tested on Supermicro X11SSH-TF using AST2400.
The SSDT contains no errors and all devices are present.
Possible TODOs:
* Add "enter config" and "exit config" bytes
* Generate support methods to enter and exit config mode
* Generate support methods to query, change or disable current
resource settings on specific LDNs
Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/superio/common/ssdt.md | 56 | ||||
| -rw-r--r-- | Documentation/superio/index.md | 3 |
2 files changed, 59 insertions, 0 deletions
diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md new file mode 100644 index 0000000000..4353cde3aa --- /dev/null +++ b/Documentation/superio/common/ssdt.md @@ -0,0 +1,56 @@ +# SuperIO SSTD generator + +This page describes the common SSDT ACPI generator for SuperIO chips that can +be found in coreboot. + +## Functional description + +In order to automatically generate ACPI functions you need to add +a new `chip superio/common` and `device pnp xx.0 on` to your devicetree. + +The xx denotes the hexadecimal address of the SuperIO. + +Place the regular LDN pnp devices behind those two entries. + +The code will automatically guess the function based on the decoded +I/O range and ISA IRQ number. + +## Example devicetree.cb + +This example is based on AST2400. + +```code +# Add a "container" for proper ACPI code generation +chip superio/common + device pnp 2e.0 on # just for the base device, not for the LDNs + chip superio/aspeed/ast2400 + device pnp 2e.0 off end + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0 + end + end + end +end +``` + +## TODO + +1) Add ACPI HIDs to every SuperIO driver +2) Don't guess ACPI HID of LDNs if it's known +3) Add "enter config" and "exit config" bytes +4) Generate support methods that allow + * Setting resource settings at runtime + * Getting resource settings at runtime + * Disabling LDNs at runtime diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md index eef4d579ef..39965fde07 100644 --- a/Documentation/superio/index.md +++ b/Documentation/superio/index.md @@ -5,3 +5,6 @@ This section contains documentation about coreboot on specific SuperIOs. ## Nuvoton - [NPCD378](nuvoton/npcd378.md) + +## Common +- [SSDT generator for generic SuperIOs](common/ssdt.md) |