src/soc/amd/cezanne: enable clock gating

Enabling clock gating for CGPLL to lower power consumption in S3
and S0i3 states. See also: Cezanne PPR chapter 7, rev 3.03.

BUG=b:185273565
TEST=iotools mmio_read32 0xfed80e2c and 0e30 show clk gating
enabled and suspend_stress_test works.

Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

0 files changed, 0 insertions, 0 deletions