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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-01-24 12:07:11 -0700
committerMartin Roth <martinroth@google.com>2018-01-31 22:12:50 +0000
commit2a5e15ce1114587ba8d111bedd40afa9e28ff622 (patch)
tree0fbdac931643ef68710db8cf41ade213edaeb56b /Documentation
parent34fa425308fdf62cd35f20d6f7ee53bce2356b56 (diff)
amd/stoneyridge: Move TValid and SmmLock to end of POST
Delay making TSEG valid until the end of POST. After the CPU setup, there are times where coreboot needs to access the SMRAM from outside of SMM. Also relocate locking of the SMM settings from the CPU init to the end of POST (or just before resuming). Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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