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author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-09-18 13:47:09 -0700 |
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committer | Martin L Roth <gaumless@gmail.com> | 2023-09-27 15:30:20 +0000 |
commit | 8e4f6e90bf96fbd34df18774f52431ac98bc4b0c (patch) | |
tree | 31a0831626c27fbc28abe6b3636a90b5c8e46b6f /Documentation | |
parent | 75f0b607fae6fb57bde7593b9c1ac926a59bf10f (diff) |
Documentation: Update 4.22 release notes with x86 .data section
Change-Id: I2d6d611df8930ad0c473489eacee9019cbdacb9e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78000
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/releases/coreboot-4.22-relnotes.md | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/Documentation/releases/coreboot-4.22-relnotes.md b/Documentation/releases/coreboot-4.22-relnotes.md index a6beccc0af..f444e80a8b 100644 --- a/Documentation/releases/coreboot-4.22-relnotes.md +++ b/Documentation/releases/coreboot-4.22-relnotes.md @@ -19,6 +19,46 @@ Update this document with changes that should be in the release notes. * This section should have full descriptions and can or should have a link to the referenced commits. +### x86: support .data section for pre-memory stages + +x86 pre-memory stages did not support the `.data` section and as a +result developers were required to include runtime initialization code +instead of relying on C global variable definition. + +Other platforms do not have that limitation. Hence, resolving it helps +to align code and reduce compilation based restriction (cf. the use of +`ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot +code). + +There were three types of binary to consider: +1. eXecute-In-Place pre-memory stages +2. `bootblock` stage is a bit different as it uses Cache-As-Ram but + the memory mapping and its entry code different +3. pre-memory stages loaded in and executed from Cache-As-RAM + (cf. `CONFIG_NO_XIP_EARLY_STAGES`). + +eXecute-In-Place pre-memory stages (#1) relies on a new ELF segment as +the code segment Virtual Memory Address and Load Memory Address are +identical but the data needs to be linked in cache-As-RAM (VMA) but to +be stored right after the code (LMA). + +`bootblock` (#2) also uses this new segment to store the data right +after the code and it loads it to Cache-As-RAM at runtime. However, +the code involved is different. + +Not eXecute-In-Place pre-memory stages (#3) did not really need any +special work other than enabling a .data section as the code and data +VMA / LMA translation vector is the same. + +Related important commits: + +- c9cae530e5ac54c5b3639d0d555966ca5cad65ff ("cbfstool: Make add-stage + support multiple ignore sections") +- 79f2e1fc8b6192e96f99c05f71baeb77d4633d40 ("cbfstool: Make add-stage + support multiple loadable segments") +- b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data section + support for pre-memory stages") + ### Toolchain updates * Upgrade GMP from 6.2.1 to 6.3.0 |