Documentation/Intel/Board: Add Galileo checklist

Add the Galileo implementation checklist. TEST=None Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
author: Lee Leahy <leroy.p.leahy@intel.com> 2016-05-30 17:09:09 -0700
committer: Leroy P Leahy <leroy.p.leahy@intel.com> 2016-06-02 02:47:29 +0200
commit: 40b41bc7992632c696201e84192192e28f7fdfa6 (patch)
tree: 7d583c2f7638fdd268a93f25cd0a7e6bc33004fa /Documentation
parent: 1bfcc843ff18653fc42fff06c22869406ff52677 (diff)
2 files changed, 131 insertions, 0 deletions
diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html
new file mode 100644
index 0000000000..3c33bb4a2a
--- /dev/null
+++ b/Documentation/Intel/Board/Galileo_checklist.html
@@ -0,0 +1,130 @@
+<html>
+<head>
+<title>Galileo Implementation Status</title>
+</title>
+<body>
+<h1>Galileo Implementation Status: 2016/05/31</h1>
+<table border=1>
+<tr><th colspan=2>romstage: 65% Done</th></tr>
+<tr><th>Type</th><th>Routine</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>car_mainboard_post_console_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>car_mainboard_pre_console_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_post_console_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_pre_console_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>fill_power_state</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_check_ec_image</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_fill_spd_data</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_memory_init_params</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>mainboard_romstage_entry</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_save_dimm_info</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>migrate_power_state</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_get_current_with_version</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_stash_data_with_version</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>print_fsp_info</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>raminit</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>ramstage_cache_invalid</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>report_memory_config</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>romstage_common</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>set_max_freq</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>setup_stack_and_mtrrs</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_memory_init_params</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>timestamp_get</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vboot_platform_prepare_reboot</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>verstage_mainboard_init</td></tr>
+</table>
+<br>
+<table border=1>
+<tr><th colspan=2>ramstage: 55% Done</th></tr>
+<tr><th>Type</th><th>Routine</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>acpi_create_serialio_ssdt</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>fw_cfg_acpi_tables</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>lb_board</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>lb_framebuffer</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_silicon_init_params</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_suspend_resume</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mirror_payload</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>northbridge_smi_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>nvm_mmio_to_flash_offset</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_bios_version</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_manufacturer</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_product_name</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_serial_number</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_set_uuid</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_silicon_init_params</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>soc_fill_acpi_wake</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_silicon_init_params</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>soc_skip_ucode_update</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_get</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_tick_freq_mhz</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>wifi_regulatory_domain</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>write_smp_table</td></tr>
+</table>
+<br>
+</body>
+</html>
diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html
index 36394192f6..cdc8fda85f 100644
--- a/Documentation/Intel/Board/galileo.html
+++ b/Documentation/Intel/Board/galileo.html
@@ -17,6 +17,7 @@
         <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li>
         <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li>
         <li><a target="_blank" href="board.html">Board</a> support</li>
+        <li><a target="_blank" href="Galileo_checklist.html">Implementation Checklist</a></li>
       </ul>
     </td>
   </tr>
author	Lee Leahy <leroy.p.leahy@intel.com>	2016-05-30 17:09:09 -0700
committer	Leroy P Leahy <leroy.p.leahy@intel.com>	2016-06-02 02:47:29 +0200
commit	40b41bc7992632c696201e84192192e28f7fdfa6 (patch)
tree	7d583c2f7638fdd268a93f25cd0a7e6bc33004fa /Documentation
parent	1bfcc843ff18653fc42fff06c22869406ff52677 (diff)