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| author | Christian Walter <christian.walter@9elements.com> | 2020-03-11 18:04:58 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-04-09 21:49:01 +0000 |
| commit | b2f8ce7591c80a199d610aad3067e01529c859a1 (patch) | |
| tree | 12e327aa85c747cc8f02578373e55023ec286ffa /Documentation | |
| parent | 6670f44cd0aec048ee881e8c9a38124cb44b2207 (diff) | |
soc/intel/cannonlake: Steal no memory for disabled IGD
Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct'
to do it like this, otherwise the FSP would always allocate memory for
the IGD even if it is disabled. In addition the FSP enables the graphics
panel power even if no IGD is present which leads to a crashing FSP.
Thus, if no IGD is present we switch off the panel via UPDs.
Refer to this issue on IntelFSP for details:
https://github.com/IntelFsp/FSP/issues/49
Tested on:
* CFL platform with IGD
* CFL platform without IGD
Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/soc/intel/fsp/index.md | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 769b98b4fc..912c44beea 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -45,6 +45,11 @@ those are fixed. If possible a workaround is described here as well. * Workaround: Disable internal UART manually after calling FSP * Issue on public tracker: [Issue 10] +### CoffeeLakeFsp +* Disabling the internal graphics causes a crash in FSP-M + * 7.0.68.40 and older version + * Workaround: Set "tconfig->PanelPowerEnable = 0" + * Issue on public tracker: [Issue 49] ## Open Source Intel FSP specification @@ -72,4 +77,5 @@ those are fixed. If possible a workaround is described here as well. [Issue 22]: https://github.com/IntelFsp/FSP/issues/22 [Issue 35]: https://github.com/IntelFsp/FSP/issues/35 [Issue 41]: https://github.com/IntelFsp/FSP/issues/41 +[Issue 49]: https://github.com/IntelFsp/FSP/issues/49 |