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authorRonak Kanabar <ronak.kanabar@intel.com>2020-03-04 19:03:47 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-03-11 14:38:17 +0000
commit35d78437991a60882f52dcfe0f653966f10041ff (patch)
tree5dd9ccceec236ba663a24f12a1f69fc74639a234 /Documentation
parent840bef061fca0ee40619e43e75ab073e9dab2d0a (diff)
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly. BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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