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author | Subrata Banik <subrata.banik@intel.com> | 2021-11-17 15:35:05 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2021-11-20 17:49:25 +0000 |
commit | b2e8bd83647f664260120fdfc7d07cba694dd89e (patch) | |
tree | 4ed4903ef9ea0cd95c0b224d20220d6bd9d18960 /Documentation/tutorial | |
parent | 8c45f236bc74a12819c4bc09a4b3e6d52bee3066 (diff) |
soc/intel/alderlake: Hook up common code for thermal configuration
Thermal configuration registers are now located behind PMC PWRMBASE
for Alder Lake Point PCH. Hence, ADL SoC to select
SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold
is being set as per mainboard provided `pch_thermal_trip`.
Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.
BUG=b:193774296
TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior
to FSP-S shows that registers are now programmed based on
'pch_thermal_trip' and lock register BIT31 is set.
Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59271
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/tutorial')
0 files changed, 0 insertions, 0 deletions