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| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-09-13 18:41:05 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-19 23:20:00 +0000 |
| commit | 7f00965209c0c48a6e060d435d07f463f869d532 (patch) | |
| tree | 9cc5fbbd28953d4522b7284c3df6bef92d06e713 /Documentation/technotes | |
| parent | 67fb347668eb9aa85936daf140af72c4384cf5f5 (diff) | |
mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT table
Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'Documentation/technotes')
0 files changed, 0 insertions, 0 deletions