summaryrefslogtreecommitdiff
path: root/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md
diff options
context:
space:
mode:
authorCliff Huang <cliff.huang@intel.corp-partner.google.com>2022-04-28 18:55:48 -0700
committerMartin L Roth <gaumless@tutanota.com>2022-06-18 04:35:37 +0000
commitedf71a08b4cb7bd8683344aa4ad301f1526289c2 (patch)
treef25e916dba05240397eaf1f62256e00bdd50371a /Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md
parent74ed2a5d609165dd1279d91d69dc811b59404d2e (diff)
soc/intel/alderlake: Skip PCIe source clock assignment if incorrect
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip for enabled root port that does not have clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md')
0 files changed, 0 insertions, 0 deletions