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authorRaul E Rangel <rrangel@chromium.org>2020-06-11 16:57:23 -0600
committerFelix Held <felix-coreboot@felixheld.de>2020-06-18 16:43:09 +0000
commit34fb9399de46574b4a6d8a3a822f430061216137 (patch)
tree9887ada2ad7dc98121383f035e6fae35925c4325 /Documentation/superio/nuvoton/npcd378.md
parentef3395d990bbf1118a8d4e367a986bdbc92b1820 (diff)
soc/amd/picasso: Add ability to enable/disable UART to device tree
If we are not using the UARTs or they don't have the correct GPIOs configured we should let the mainboard disable them. BUG=b:153001807 TEST=Dump SSDT and see UART device is disabled Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifc04e36e0ebe5cce4b6cc228c7174dc76f2ffa4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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