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| author | Jan Samek <jan.samek@siemens.com> | 2022-12-01 14:52:51 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-12-17 20:39:44 +0000 |
| commit | a1a8f58a0713dad8bc621daf180790504b897dda (patch) | |
| tree | 0011a15913fdc835de5d1404ae28caeefdc41e20 /Documentation/superio/index.md | |
| parent | a2035cc4d08b0894121024376a8e06749c911dfb (diff) | |
mb/siemens/mc_ehl3/devicetree.cb: Adapt PCIe root port settings
Based upon hardware differences from mc_ehl2, disable RP7
and enable RP3 and RP5.
Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/superio/index.md')
0 files changed, 0 insertions, 0 deletions