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authorAaron Durbin <adurbin@chromium.org>2016-07-12 23:39:51 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-13 21:58:22 +0200
commit1318e88352d7b20661adec82769f46308471d739 (patch)
treeb16ca346ca2f11952699befaa1ac17c14ece7457 /Documentation/submodules.txt
parentc79101ab84be4ee145917b64c1e9ea23461f82c5 (diff)
soc/intel/apollolake: add initial ITSS support
The interrupt and timer subsystem (ITSS) sits between the APIC and the other logic blocks. It only supports positive polarity events, but there's a polarity inversion setting for each IRQ such that it can pass the signal on to the APIC according to the expected APIC redirection entry values. This support is needed in order for the platform/board to set the expected interrupt polarity into the APIC for gpio signals. BUG=chrome-os-partner:54955 Change-Id: I50ea1b7c4a7601e760878af515518cc0e808c0d1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15647 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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