diff options
| author | Patrick Georgi <pgeorgi@google.com> | 2021-11-03 10:11:35 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2021-11-19 18:26:00 +0000 |
| commit | ef164196cbe6d703366b61070b6b6f1a6bc0038f (patch) | |
| tree | 18e4ee402faea6b171d2c5d2e264f46a7af0cdea /Documentation/soc | |
| parent | 7dce19080889955576f8fd197658077aced96a96 (diff) | |
Documentation: Add some notes about how to integrate FSP
While we don't _want_ FSP, we can't get around it sometimes. But when
using it, we can still try to establish best practices to make life
easier for everybody.
Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'Documentation/soc')
| -rw-r--r-- | Documentation/soc/intel/fsp/index.md | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 912c44beea..feeb5e9433 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -2,6 +2,18 @@ This section contains documentation about Intel-FSP in public domain. +## Integration Guidelines + +Some guiding principles when working on the glue to integrate FSP into +coreboot, e.g. on how to configure a board in devicetree when that affects +the way FSP works: + +* It should be possible to replace FSP based boot with a native coreboot + implementation for a given chipset without touching the mainboard code. +* The devicetree configures coreboot and part of what coreboot does with the + information is setting some FSP UPDs. The devicetree isn't supposed to + directly configure FSP. + ## Bugs As Intel doesn't even list known bugs, they are collected here until those are fixed. If possible a workaround is described here as well. |