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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-03-03 01:58:17 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-11 19:57:44 +0000 |
| commit | f787e8714589da232e198ca5bdcf602fe923b603 (patch) | |
| tree | 6e5613c9e86f92a08bcdd56da4809df08bdfaba6 /Documentation/soc/qualcomm | |
| parent | ccde6be13a64f369da61c70be0221d0bc24f0fe2 (diff) | |
mb/intel/tglrvp: Enable Hybrid storage mode
BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Diffstat (limited to 'Documentation/soc/qualcomm')
0 files changed, 0 insertions, 0 deletions