diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-18 19:51:57 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-19 12:56:10 +0000 |
| commit | a9112169267b209e72d5cf274fddb53f5febd7d2 (patch) | |
| tree | 014c8b7c436e7d622cf9d31c47fb0207f3abc95d /Documentation/soc/intel | |
| parent | 6098da9ea81067b91e67793aac05bc534edd5c3b (diff) | |
docs: intel fsp: add memory retraining bug on SPS systems
FSP2.0 forces MRC retraining on cold boot on Intel SPS systems.
Change-Id: I3ce812309b46bdb580557916a775043fda63667f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'Documentation/soc/intel')
| -rw-r--r-- | Documentation/soc/intel/fsp/index.md | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index aac7b35a50..769b98b4fc 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -34,6 +34,11 @@ those are fixed. If possible a workaround is described here as well. * Workaround: none * Issue on public tracker: [Issue 22] +* MRC forces memory re-training on cold boot on boards with Intel SPS + * Releases 3.7.1, 3.7.6 + * Workaround: Flash Intel ME instead of SPS + * Issue on public tracker: [Issue 41] + ### BraswellFsp * Internal UART can't be disabled using PcdEnableHsuart* * Release MR2 @@ -66,4 +71,5 @@ those are fixed. If possible a workaround is described here as well. [Issue 15]: https://github.com/IntelFsp/FSP/issues/15 [Issue 22]: https://github.com/IntelFsp/FSP/issues/22 [Issue 35]: https://github.com/IntelFsp/FSP/issues/35 +[Issue 41]: https://github.com/IntelFsp/FSP/issues/41 |