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| author | John Zhao <john.zhao@intel.com> | 2020-05-27 23:11:19 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-30 00:42:15 +0000 |
| commit | 23e8b5b4949063319c339120f13e392a90493b58 (patch) | |
| tree | 89a760ede3520fb5ece385e3797784d5cd7b27ae /Documentation/soc/intel/fsp/index.md | |
| parent | 74b1919f1779a3a3b1a0320482784bb31234b175 (diff) | |
soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.
BUG=:b:146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/soc/intel/fsp/index.md')
0 files changed, 0 insertions, 0 deletions