diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2020-08-28 19:28:01 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-08-29 01:59:02 +0000 |
| commit | b656e9b71e2ce494568ad1389b04b7dbb085d7ee (patch) | |
| tree | ebfbe1795a768dbad962275e4ced24f17c8aaac6 /Documentation/soc/cavium | |
| parent | 07de90837363f2e4e58d08fe15ef41381f71815f (diff) | |
PCI IDs: Add PCI ID for CML DPTF/DTT PCI device
This PCI ID is required in order for the CML devices to perform
SSDT generation for DPTF.
CML Processor, EDS, Vol 1,
Table 9-5, Section 9.2.
BUG=b:158986928
BRANCH=puff
TEST=builds
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
Diffstat (limited to 'Documentation/soc/cavium')
0 files changed, 0 insertions, 0 deletions