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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2023-09-26 12:45:04 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-10-19 16:19:31 +0000 |
| commit | 180c702bb94f3af04d25be87e56415f520c301e1 (patch) | |
| tree | 8bbfec6ffb8b1538c490eb927bd047bece5e251c /Documentation/soc/amd/index.md | |
| parent | 74f5a3e8a00edb82c9766fc9edb157c32959b20d (diff) | |
soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
Within TBT PCIe, following register offsets have been updated for
production silicon. Update ASL with new offsets.
1. MPC - Miscellaneous Port Configuration Register
2. RPPGEN - Root Port Power Gating Enable
3. SMSCS - SMI/SCI Status Register
BUG=306026121
TEST= Check TBT PCIe Tunnel creation and device enumration.
Change-Id: I0497f7108ef5046c2694aece232263582514a0c5
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'Documentation/soc/amd/index.md')
0 files changed, 0 insertions, 0 deletions