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| author | Cliff Huang <cliff.huang@intel.com> | 2021-08-19 14:32:50 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-30 12:20:28 +0000 |
| commit | 73ed5991bc42caf306fd6f2b13696853b7069e02 (patch) | |
| tree | a994da5ad3ceb7e17064f5e7b50b9c3cf54f26a8 /Documentation/security | |
| parent | ced18c6777d622775170286c4a08414c40d783f2 (diff) | |
mb/intel/adlrvp_m: Fix to Enable PCIe x1 Slot
This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs.
The BDF for this PCIe slot is pci is: 0000:00:1d.0
TEST = show device command:
$ lspci -s 00:19.0
expect this:
00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/security')
0 files changed, 0 insertions, 0 deletions