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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2019-07-19 15:32:29 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-24 03:17:39 +0000 |
| commit | 4288cda2ed8a765c53a3823b4e9a53d93d78a490 (patch) | |
| tree | f57659529db8fde5a0501921ef4e03751d95e972 /Documentation/releases/coreboot-4.10-relnotes.md | |
| parent | 46445155ea21b0aa9106e12a00b9b1d89887a461 (diff) | |
soc/intel/common: Set controller state to active in GSPI init
Set the controller state to D0 during the GSPI sequence,this ensures
the controller is up and active.
BUG=b:135941367
TEST=Verify no timeouts seen during GSPI controller enumeration
sequence for CML and ICL platforms.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'Documentation/releases/coreboot-4.10-relnotes.md')
0 files changed, 0 insertions, 0 deletions