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authorRaul E Rangel <rrangel@chromium.org>2020-12-16 10:08:41 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-01-06 17:26:46 +0000
commit4e80fae2367d3a0a64ac2896dc654e0cf842fc4e (patch)
tree07769402cfa009c6148e776534f998df24b77e59 /Documentation/payloads.md
parent2f5fd1147442978264f062422812ec12f64a23a5 (diff)
soc/amd/picasso: Correctly populate the PCI interrupt line register
The PCI interrupt line registers are used as a last resort if routing can't be fetched from either ACPI or the MPTable. This change correctly sets the registers. It overrides the pirq_data set by the mainboards since the routing is fixed in AGESA. BUG=b:170595019 TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic` Verified all PCI peripherals are still functional. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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