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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-11-08 13:49:24 +0100
committerWerner Zeh <werner.zeh@siemens.com>2018-11-12 07:26:13 +0000
commit4946804f0b6536df3e7a46654c0dbbc3172b1de8 (patch)
tree291330d78456374b1799d9e4713a413469aee2a3 /Documentation/northbridge
parent04ea73ee78bceb680a2565777c4c7774c2ad1a8e (diff)
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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