soc/intel/tigerlake: Update GPIO config

GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups from coreboot so that they are mapped properly.
GPIO communities should be properly configured in GPIO_CFG and
MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured
in GPIO_CFG register while the PMC_GPP_* in pmc.h are used to
configure the MISCCFG registers.

BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. Verified that after
     setting the gpe from devicetree the GPP_EN register for
     that community gets updated setting that specific bit.
     From the iotools i checked that GPE_EN register for that
     community is updated with that specific bit set to 1.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

0 files changed, 0 insertions, 0 deletions