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authorFrans Hendriks <fhendriks@eltan.com>2018-11-19 11:59:00 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-22 15:02:23 +0000
commit613da18fecc757ed75dca97578f316b15bd3f826 (patch)
treeb35391ef83d87822201feedac1abb0cb33cb3d51 /Documentation/northbridge/intel
parent166cbdec5b042f28badedd09da1203c9a1feccfc (diff)
drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S
soc/car_setup.S is included when SKIP_FSP_CAR is enabled, but no chipset/SoC have car_setup.S available. Remove include and post_code() call always solving build errors. BUG=NA TEST=NA Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang Jin <huang.jin@intel.com>
Diffstat (limited to 'Documentation/northbridge/intel')
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