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| author | Angel Pons <th3fanbus@gmail.com> | 2018-08-20 13:32:57 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2018-08-22 07:03:13 +0000 |
| commit | fa1a07bf509bee95a9f4291c9a6fe639ae512d94 (patch) | |
| tree | 992b934f256d537fe2b07f726a6264103564b4b8 /Documentation/northbridge/intel/sandybridge/nri.md | |
| parent | 19e4f74fc4be153dda8897664f6278c0d51bbf47 (diff) | |
Documentation/northbridge/intel/sandybridge/*: fix typos
Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in
text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy
Bridge".
Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'Documentation/northbridge/intel/sandybridge/nri.md')
| -rw-r--r-- | Documentation/northbridge/intel/sandybridge/nri.md | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index 1b07ba48eb..812cd23fdb 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -3,7 +3,7 @@ ## Introduction This documentation is intended to document the closed source memory controller -hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs. +hardware for Intel 2nd Gen (Sandy Bridge) and 3rd Gen (Ivy Bridge) core-i CPUs. The memory initialization code has to take care of lots of duties: 1. Selection of operating frequency @@ -41,13 +41,13 @@ The memory initialization code has to take care of lots of duties: ``` ## (Inoffical) register documentation -- [Sandy Bride - Register documentation](nri_registers.md) +- [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection -- [Sandy Bride - Frequency selection](nri_freq.md) +- [Sandy Bridge - Frequency selection](nri_freq.md) ## Read training -- [Sandy Bride - Read training](nri_read.md) +- [Sandy Bridge - Read training](nri_read.md) ### SMBIOS type 17 The SMBIOS specification allows to report the memory configuration in use. @@ -113,7 +113,7 @@ than a board that doesn't boot at all. > **Note:** This feature is available since coreboot 4.5 Try to swap memory modules and or try to use a different vendor. If nothing -helps you could have a look at capter [Debuggin] or report a ticket +helps you could have a look at chapter [Debugging] or report a ticket at [ticket.coreboot.org]. Please provide a full RAM init log, that has been captured using EHCI debug. |