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authorMartin Roth <gaumless@gmail.com>2022-05-28 12:32:02 -0600
committerMartin L Roth <gaumless@tutanota.com>2022-05-30 04:24:57 +0000
commitbbe876250f2bc5045cc3947c024e6f70330cc9ba (patch)
treea1a647253193f108e2789416fd90eb053b4a31ac /Documentation/mainboard
parent7b9d08e8498261c0c33f3032c11752e4b75a641b (diff)
Documentation: Fix a few spelling issues
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I47add663f3021170b840203ce229acf836b7a1c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'Documentation/mainboard')
-rw-r--r--Documentation/mainboard/acer/g43t-am3.md2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/mainboard/acer/g43t-am3.md b/Documentation/mainboard/acer/g43t-am3.md
index e57009c4de..07d23c6dea 100644
--- a/Documentation/mainboard/acer/g43t-am3.md
+++ b/Documentation/mainboard/acer/g43t-am3.md
@@ -134,7 +134,7 @@ SPI_ROM1 header while the board is off and disconnected from power. There
seems to be a diode that prevents the external programmer from powering the
whole board.
-The signal assigment on the header is identical to the pinout of the flash
+The signal assignment on the header is identical to the pinout of the flash
chip. The pinout diagram below is valid when the PCI slots are on the left
and the CPU is on the right. Note that HOLD# and WP# must be pulled high
(to VCC) to be able to flash the chip.