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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-08-05 08:23:52 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2019-08-06 12:04:01 +0000
commitc4d56d668f682f7d0d77a2e02f4728b1299f406e (patch)
tree32a001bc825b8eee401f3e82996739d08101b719 /Documentation/mainboard
parentbe207b10988cd81b0f8da16cac958e8456987a69 (diff)
Documentation: Advertise support for OpenSBI
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
Diffstat (limited to 'Documentation/mainboard')
-rw-r--r--Documentation/mainboard/sifive/hifive-unleashed.md1
1 files changed, 0 insertions, 1 deletions
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
index 495dade212..4dbbf0e073 100644
--- a/Documentation/mainboard/sifive/hifive-unleashed.md
+++ b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -17,7 +17,6 @@ The following things are still missing from this coreboot port:
- Provide serial number to payload (e.g. in device tree)
- Implement instruction emulation
- Support for booting Linux on RISC-V
-- Add support to run OpenSBI payload in m-mode
- SMP support in trap handler
## Configuration