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authorJamie Ryu <jamie.m.ryu@intel.com>2024-11-05 12:02:26 -0800
committerSubrata Banik <subratabanik@google.com>2024-11-08 19:10:01 +0000
commit7e0c771c50abbab6ff28483f75c5e3ae19de3301 (patch)
treed2cb6ab380e0863ebf3ec353c97be5384af19a4b /Documentation/mainboard/ti
parent89e6640bf911b607bb169984ee5f20be352d79fa (diff)
soc/intel/pantherlake: Update power limits config
This updates power_limits_config for Panther Lake U and H. Source: Intel PTL PDG 813278 Intel PTL FSP Power limit profiles table BUG=b:357011633 TEST=Build fatcat and boot with Panther Lake SoC and RVP. Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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