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| author | Naresh Solanki <naresh.solanki@9elements.com> | 2024-10-11 22:51:38 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-10-16 15:27:03 +0000 |
| commit | 1d18513ad5d10034effb0b10e7db11487fa7e6cf (patch) | |
| tree | 8fc2505c8d8146784a3a78312132ea4b93dcb6fa /Documentation/mainboard/supermicro/x9sae.md | |
| parent | d11ee4952194934ebdea4ef5481b9095958eb247 (diff) | |
soc/intel/xeon_sp: Allow Memory POR independent of RMT
TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs.
Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'Documentation/mainboard/supermicro/x9sae.md')
0 files changed, 0 insertions, 0 deletions