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| author | Julian Schroeder <julianmarcusschroeder@gmail.com> | 2021-05-11 10:44:13 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-26 15:15:53 +0000 |
| commit | d2f3308ad7efd01a2d23749aa4ccc6bc5efc8a56 (patch) | |
| tree | 2200586bb2ba0a5dabf6acf60dcfedcdc40adbe0 /Documentation/mainboard/pcengines/apu1_spi.jpg | |
| parent | e84a014ee6121424593ded21591c3e759847b784 (diff) | |
soc/amd/cezanne: add support for the changed AMD FSP API for USB PHY
The AMD FSP is using a new structure for USB and USB C phy settings.
This patch removes old, unused structures, adds the new one and
enables the devicetree interface for it.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'Documentation/mainboard/pcengines/apu1_spi.jpg')
0 files changed, 0 insertions, 0 deletions