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| author | John Zhao <john.zhao@intel.com> | 2020-08-02 11:29:59 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-08-12 19:43:07 +0000 |
| commit | 90883287b5db3c022bf45d98a00f88b4b9b7c055 (patch) | |
| tree | 00d1872fb9e9c80d0b66460fc9d823bd27e22a31 /Documentation/mainboard/pcengines/apu1_spi.jpg | |
| parent | 1d7ba15aa2e3a3ee9130101977405ef866bd7f79 (diff) | |
mb/intel/tglrvp: Add interrupt _CRS under CREC scope
Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15
assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as
active low and level interruptible for EC sync interrupt configuration.
BUG=None
TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC
current resource settings.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/mainboard/pcengines/apu1_spi.jpg')
0 files changed, 0 insertions, 0 deletions