diff options
author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-08-10 16:15:14 -0700 |
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committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-09-30 03:08:22 +0000 |
commit | 8c678cf46a2bc9716a84609615b602422a233a9e (patch) | |
tree | 9071de3323980493c3a57fe15e413ef08dfd3ac9 /Documentation/mainboard/opencellular/elgon.md | |
parent | 7de4bb5172134fb801d0c087a84013b58b35d9d2 (diff) |
mainboard/opencellular/elgon: Add mainboard support
Tested on Elgon EVT board and boots into GNU/Linux.
TODO:
* Add hard reset function for VBOOT.
* Add EC code
* Add SPI flash write protection
Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'Documentation/mainboard/opencellular/elgon.md')
-rw-r--r-- | Documentation/mainboard/opencellular/elgon.md | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/Documentation/mainboard/opencellular/elgon.md b/Documentation/mainboard/opencellular/elgon.md new file mode 100644 index 0000000000..37d05e64f5 --- /dev/null +++ b/Documentation/mainboard/opencellular/elgon.md @@ -0,0 +1,72 @@ +# Elgon + +This page describes how to run coreboot on the [Elgon] compute board +from [OpenCellular]. + +## TODO + +* Add hard reset control + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | W25Q128 | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + +### External programming + +The EVT board does have a pinheader to flash the SOIC-8 in circuit. +Directly connecting a Pomona test-clip on the flash is also possible. + +TODO: pinout + +**Total board view of EVT** + +![][elgon1] + +[elgon1]: elgon1.png + +**Closeup view of SOIC-8 flash IC, programming pin header and +USB serial connector of EVT** + +![][elgon2] + +[elgon2]: elgon2.png + +## Technology + +```eval_rst ++---------------+----------------------------------------+ +| SoC | :doc:`../../soc/cavium/cn81xx/index` | ++---------------+----------------------------------------+ +| CPU | Cavium ARMv8-Quadcore `CN81XX`_ | ++---------------+----------------------------------------+ + +.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html +``` + +[Elgon]: https://github.com/Telecominfraproject/OpenCellular +[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/ +[flashrom]: https://flashrom.org/Flashrom |