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| author | Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-11-28 02:05:52 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-19 05:51:18 +0000 |
| commit | a86c198cd5fec0e27a94c620c08e4a440f7d433f (patch) | |
| tree | 92c91ad99dd6da1cd0f2dd97b095c9fc23d118c6 /Documentation/mainboard/intel | |
| parent | 9622024a95e140fcbf8a28d131688b8db039b2c8 (diff) | |
Documentation/../../kblrvp11: Add RVP11 documentation
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd
Reviewed-on: https://review.coreboot.org/c/29859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Diffstat (limited to 'Documentation/mainboard/intel')
| -rw-r--r-- | Documentation/mainboard/intel/kblrvp11.md | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/Documentation/mainboard/intel/kblrvp11.md b/Documentation/mainboard/intel/kblrvp11.md new file mode 100644 index 0000000000..5b0496d121 --- /dev/null +++ b/Documentation/mainboard/intel/kblrvp11.md @@ -0,0 +1,79 @@ +# Intel Kaby lake RVP11 + +## Specs + +* 1 SATA cable connect +* 1 SATAe direct +* 2 USB2.0 connector +* 4 USB3.0 connector +* 1 Gigabit Ethernet +* 1 x4 PCIe slot +* 1 x1 PCIe slot +* 1 X16 PEG slot +* UART debug DB9 connector +* 4 DIMMS with DDR4 memory +* SPI flash +* Audio Jack +* PS2 Keyboard and Mouse +* Display: HDMI, DP, VGA + +## Target Audience + +* OEMs, internal only + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q128FV | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +``` + +### Instruction to flash coreboot to SPI + +### Internal programming + +The SPI flash can be accessed internally using [flashrom]. +The following command is used to flash BIOS region. + +```bash +$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all +``` + +### External programming + +1. Dediprog SF600 with adapter B is used. +2. Make sure power supply is disconnected from board. +3. Connect Dediprog SF600 to header at J7H1. +4. Ensure that "currently working on" is in "application memory chip 1" +5. Go to "file" and select the .rom file (16 MB) to program chip1. +6. Execute the batch operation to erase and program the chip. + +## Technology + +```eval_rst ++------------------+---------------------------------------------------+ +| CPU | Kaby lake H (i7-7820EQ) | ++------------------+---------------------------------------------------+ +| PCH | Skylake PCH-H (called SPT-H) | ++------------------+---------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+---------------------------------------------------+ +``` + +[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf +[flashrom]: https://flashrom.org/Flashrom |